Anti-fuse memory is one type of one-time programmable (OTP) memory in which the device can be permanently programmed (electrically) with data once. This data is programmed by an end user for a particular application. There are several types of OTP memory cells which can be used. OTP memories provide users with a level flexibility since any data can be programmed.
Anti-fuse memory can be utilized in all one time programmable applications where it is desired to provide pre-programmed information to a system, in which the information cannot be modified. One example application includes radio-frequency identification (RFID) tags. RFID tagging applications are gaining more acceptance in the industry, particularly in sales, security, transport, logistics, and military applications for example. The simplicity and full CMOS compatibility anti-fuse memory allows for application of the RFID tag concept to integrated circuit manufacturing and testing processes.
FIG. 1 is a circuit diagram illustrating the basic concept of an anti-fuse memory cell, while FIGS. 2 and 3 show the planar and cross-sectional views respectively, of the anti-fuse memory cell shown in FIG. 1. The memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of an anti-fuse device 12. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of the anti-fuse device 12 for programming the anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer, is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard complementary metal-oxide-semiconductor (CMOS) processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses must be reliable while simple to manufacture with a low cost CMOS process.
Most systems require a period of time to power up, to ensure that the voltages applied to the components of the system have reached a stable level sufficient to ensure proper operation thereof. There are many known circuits in the art for detecting a voltage supply reaching a predetermined level. However, due to variables such as operating temperature, a simple detection of the supply voltage reaching the predetermined level may not be sufficient for ensuring that the device can properly operate.
It is, therefore, desirable to provide a power up detection system and method which reliably confirms that the OTP memory has completed power up and will thus function as expected.